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G8MNY  > TECH     09.07.18 10:03l 45 Lines 1811 Bytes #999 (0) @ WW
BID : 28247_GB7CIP
Read: GUEST
Subj: Mono Stable Revisited
Path: HB9ON<IW2OHX<UA6ADV<CX2SA<GB7CIP
Sent: 180709/0801Z @:GB7CIP.#32.GBR.EURO #:28247 [Caterham Surrey GBR]
From: G8MNY@GB7CIP.#32.GBR.EURO
To  : TECH@WW

By G8MNY                                         (New Jan 16)
(8 Bit ASCII graphics use code page 437 or 850, Terminal Font)

I needed a timer to timeout a 0V ON signal, on a Tx after a few minutes for RDS
Trafic flag. I had done it before with a 555 timer & input & output
conditioning inverters, all far too complex really. So I had a re-think on the
basic 2 transistor circuit, & came up with this simple junk box design.

A simular circuit can be used on PTT line of most Tx to limit key up time!

+5-20V >컴쩡컴컫컴컴컴컴컴컴컴컫컴컴컴커
         10k                 33k     1k
             2M2                    __
              쿝                LED=\_/      Time  
                        BC337쳐     쳐컴컴>Limited
Low        +             T1/     /BC337   Low Output
Input >컴컨캑쳐좔10K컫컴>쳐캑   읕컴 T2
          C 100u    ===  *   \e     \e 
                  u1                 
0V >컴컴컴컴컴컴컴컴컨컴컴컴컴컨컴컴컴컨컴컴컴>

With no input, T1 is on & T2 held off. The 33k must be low enough to get 0V out
of T2 with required load, & the 2M2 must be low enough for T1 to turn of T2.
Higher gain transistor like the BC109c (900 Hfe) can be used for T1 with R of
10M for longer times, if the cap C is realy low leakage.  

With the input low, a negative voltage equal to the power rail, is appled to
T1's base, holding it off for around 200 seconds. The CR time constant of 2M2
with the 100uF cap sets the time, but a leaky C will only shorten the time
slighty in this circuit.

T1s Base 10K & u1 give basic false pulse/RF imunity.

On 5V the diode (* 1N4148) can be omitted as it is not needed to protect T1's
base from going too negative & damaging T1.



Why Don't U send an interesting bul?

73 De John, G8MNY @ GB7CIP


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